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CMT-Slide2

Shown here is a block diagram of a typical CMT unit on an RX MCU. An RX MCU might have multiple CMT units. It should be noted that a single CMT unit contains two CMT timer channels. These channels share a single register CMSTR containing each channels’ start bits. The bottom right of this diagram shows that the CMT sits on the peripheral bus and that the clock used for driving the timer is generated from a pre-scaled peripheral clock ranging from divide by 8 to divide by 512. The pre-scalar selection is determined by a field in the CMCR register. The period of the timeout is controlled by resetting the 16-bit counter value CMCNT when it equals the value set in the compare register CMCOR. When the counter is reset by the compare match value, an event CMI is sent to the interrupt control unit. This event can generate an interrupt or the interrupt request state can be polled by software. There is a separate CMI interrupt for each CMT channel. Finally, note that the CMT’s have no external pins associated with them. They are completely internal resources that are typically used to generate periodic RTOS pre-emptions, software timeout notifications, or to trigger a DMAC or DTC transfer.

PTM Published on: 2011-12-01