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This figure here shows the SCTimer/PWM block diagram with its major components. The top left section is dedicated to the clock inputs, which includes two pre-scale registers, one for each 16-bit counter. These can be used to reduce the clock rate at which the timer runs. The SCTimer/PWM also has an option for using an external clock source for the counters. At the bottom left, the counters, together with the match logic, provide the basic timer functionality, which means comparing the counter register to a specific value, or capturing the counter value at a certain instant in time when a condition on a trigger input signal is satisfied. The advanced part is provided in the right hand side of the diagram, the event generation logic. This block is used to define the hardware events, which can be dependent on inputs, match values, outputs, or also a combination of them. The defined events also depend on the state logic, and can transition the timer to a different state in the associated flow diagram. All defined events are able to drive outputs, and can be configured to generate interrupts to the CPU, or transfer requests to the on-chip DMA controller.
