The LPC1800 is based on the latest revision of the ARM Cortex-M3 core. The M3 core was designed for both performance and power in embedded applications. It utilizes a Harvard Architecture with a three stage pipeline and uses both Thumb2 and Thumb instructions. It supports hardware divide and single cycle multiply and offers fast, deterministic interrupts with the built in NVIC or nested vectored interrupt controller. The M3 core also has advanced integrated low power modes and the optional memory protection unit is included in all LPC1800 products. The memory protection unit can improve the reliability of an embedded system by protecting critical data used by an operating system or user applications. A wake up interrupt controller and JTAG trace are also included.