The clock dividers available in the product portfolio have the option of dividing by one through six, eight, and sixteen. While some dividers have a dedicated division ratio with one input and one output, many clock dividers are capable of generating a clock tree. These parts have multiple banks for different output frequencies and each bank has an integrated fan-out which provides more design flexibility. Since these clock dividers are non-PLL based, the typical jitter is sub-500 fS. For cable and backplane applications, Microchip offers pre-emphasis drivers and equalization receivers that can drive and receive signals over long transmission mediums, including FR4 PCB traces. The EQ receivers do an excellent job of improving the eye pattern of a significantly degraded signal even at 10 Gbps. Finally, also available from Microchip are delay lines with 5 pS and 10 pS per step resolution. For example, the SY89297U delay line, with 5 pS per step delay has 1023 steps to provide total of 5 nS delay per channel.