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RS-Slide20

The RS-485 bus is considered idle when there is no data being transmitted, and the idle state for most RS-485 networks is a high logic level. The first low bit after an idle state is assumed to be a message start bit, and this signal prompts a controller to service the message. Thus it is desirable for an inactive bus to remain in the high logic state, thereby ensuring that all receiver outputs properly present an idle state to their microcontrollers. In this regard, terminated multi-point networks suffer from a major design issue. When no transmitter is driving the bus, the termination resistors collapse the bus to a 0V differential. Since the RS-485 standard defines the logic thresholds at plus and minus 200mV, a 0V differential is an undefined level. Therefore a receiver output may be high, or low, or may even oscillate. An erroneous low level, or an oscillation, may be interpreted as start bits, so the controller may waste valuable processing time servicing phantom messages. One solution to this problem is to add bus biasing resistors – as shown on the diagram on this slide – to ensure that a floating bus is held in a logic 1 state. A pull-up on the non-inverting A node, and a pull-down on the inverting B node develops a positive differential voltage to keep all the receivers outputting the proper idle state. But adding bus biasing complicates the design. The smaller the bus biasing resistor value, the higher the idle voltage – which gives better noise immunity - but the transmitter’s differential output voltage degrades due to the extra load. This can be a difficult tradeoff to balance. Additionally, bus biasing reduces the maximum number of devices that can be on the bus, because the bias resistors load the active driver just like additional transceivers do. Bias resistors also increase the system power consumption because of the direct and relatively low resistance path from Vcc to GND. Typical bias resistors are 300 Ω to 1 kΩ, so with a 3.3V supply there is a DC current of 1.6 to 5mA. To block this DC current one can use an AC termination scheme, which is a capacitor in series with each termination resistor, but this further complicates the design.

PTM Published on: 2016-01-04