To transfer data the user must know in which direction (in or out) the data is to be latched, which clock edge the data is to be latched, and how much data is to be transferred. All options are defined in AN_108, but the key rule to remember is that the clock is only running when data is being transferred and the idle state of the clock determines which clock edge may be used to clock data in or out. If the clock starts at an idle state of logic 0; data can be clocked out on a –ve clock edge, and in on a +ve clock edge. If the clock starts at an idle state of logic 1; data can be clocked out on a +ve clock edge, and in on a -ve clock edge.