The modulator contains a PWM comparator that compares the timing ramp to a control voltage (VC). The comparator puts out a constant frequency, variable pulse width signal that controls the power stage. At the beginning of the switching period (T), this signal is high, turning on the NMOS (or PMOS) switch. When the timing ramp exceeds VC, this signal goes low, turning off the switch. The modulator gain is a function of the ramp amplitude (VP). The power stage consists of the NMOS output switch, commutating diode, and the LC network. The gain of this stage is a function of VIN and this is a very important item to note. In the diagram shown here, the feedback, error-amp, and compensation are represented by generic control system symbols. This is because there are two different error-amp circuits used for implementing this section, and each circuit introduces a unique characteristic to the regulator loop.