These equations describe the loop gain of a voltage mode buck regulator. The modulator and power stage gain increases directly with the input voltage (VIN). Increasing the amplitude of the timing ramp (VP) reduces the gain because as the slope of VP increases, it takes a larger change in the output of the error amplifier to result in the same duty cycle change. This allows the regulator’s DC loop gain to be much higher than the mid-band gain. The frequency dependent term is the transfer function of the LC network. This network has a double pole due to the inductor and output cap, and it has a zero resulting from the output capacitor C and RC, the ESR of the capacitor.