For this device, the user may also select boot mode between flash and SRAM. For other devices, the user may configure additional fuses controlling the on-chip oscillators, disable the reset pin, and select the appropriate brownout detector voltage. Finally, security bits may be set and lock the target from being accessed by customers and competitors through the debug interphase. Just note that setting these bits also prevents performing any in-circuit debugging. Even though it can be unlocked by a complete chip erase later on, it is more practical to just keep the device unlocked for the internal development stages. Advanced users may want to optimize the JTAG clock setting, disable the external reset function of the reset pin, or enumerate the JTAG enabled device for boards where more than one JTAG enabled chip is connected in a daisy chain. All of these functions are performed from the new Device Programming dialogue. For now, the user is satisfied with just clicking the ”Program” button and confirming that everything went OK.