This slide shows a timing diagram of the accumulation process. Shown on the left is the accumulator block diagram with an applied FTW along with the system clock. The system clock appears at the bottom of the timing diagram. It has a period, Ts, corresponding to its frequency Fs. The blue trace in the diagram depicts the output value of the accumulator over time. Because the output of an N-bit accumulator can represent 2^N unique codes, the value is called Ts the capacity of the accumulator and denoted with the variable C. That is, the accumulator can only represent numeric values from zero to C minus one. A value of C or greater constitutes an overflow. The horizontal dashed lines indicate the upper and lower bounds of the accumulator output, C and zero, respectively. Starting  at the left side of the diagram, the accumulator is initially at 0. Proceeding from left to right, there occur successive rising edges of the system clock. Each rising edge results in an accumulation of the FTW. The accumulator output increments in a staircase manner, as depicted by the blue trace. Eventually, however, the accumulator output grows to the point where the next rising edge of the system clock and subsequent accumulation of the FTW causes the accumulator to reach or exceed the upper limit, C. That is, the accumulator will overflow. The overflow amount is a remainder as shown by the red area above the C limit. When the accumulator overflows it rolls over for a new start. However, rather than automatically starting at zero, it starts with the value of the remainder, as shown by the red area above the zero limit, and resumes the accumulation process beginning with that remainder value. It is interesting to note that some FTW values always result in a remainder of zero at the overflow point. FTWs that exhibit this behavior are those that are an exact power of two. This is because such FTWs divide evenly into C. All other FTWs yield their own unique pattern of consecutive non-zero remainders. In fact, the pattern of remainders behaves like the output of an accumulator possessing FTW as its capacity and the value of the first remainder in the pattern as its FTW. However, there is always a point at which the remainder pattern will yield a value of 0. In fact, for a given FTW, the same number of system clock periods will occur between successive occurrences of a zero remainder. Curiously, the number of system clock periods between successive occurrences of a zero  remainder will always be at least one but never greater than C. The time interval between successive occurrences of a zero remainder is known as the grand repetition period. The concept of an overflowing accumulator is essential to understanding how an accumulator establishes the output frequency of a DDS.