An accumulator is a circuit comprised of a bank of latches with a digital adder connected in a feedback configuration. All the latches share a common clock input, namely the system clock. Hence, each latch transfers the binary value at its D input to its Q output synchronously. That is, all latches transition in unison on each rising edge of the system clock. The number of latches in the accumulator constitutes the width of its input and output buses, an accumulator with N latches occupies an N-bit bus. An N-bit bus forms an N-bit digital word, which is capable of representing 2^N unique codes corresponding to numeric values ranging from zero to 2^N minus one. In the diagram shown on this slide, the N-bit bus is organized such that the top latch handles the most significant bit (MSB) of the N-bit word, while the bottom latch handles the least significant bit (LSB). The remaining latches handle bits with decreasing weight from top to bottom. The N-bit output bus of the accumulator connects to one input of an N-bit adder, the other N-bit input of the adder accepts the FTW. The N-bit output of the adder is distributed to the D input of the N latches.  As an example, with the initial condition of all latches cleared and an N-bit FTW with a value of five, the accumulator output is zero, which appears at the top of the adder. The adder output is the sum of its two inputs, five and zero, which results in five. Therefore, the value five, represented by N-bits appears at the input to the N latches. On the first rising edge of the system clock, the five at the latch inputs gets transferred to the latch outputs and the accumulator output now is five. Also, the value five appears at the top of the adder. The adder sums the feedback value of five with the unchanged FTW value of five resulting in a value of ten at the adder output and a value of ten appears at the input of the N latches. On the second rising edge of the system clock, the ten at the latch inputs gets transferred to the latch outputs. The accumulator output is ten, whereas it was five prior to the second rising edge of the system clock. Subsequent rising edges of the system clock cause this process to repeat. The result is that the accumulator output increments by five (the value of the FTW) with each new rising edge of the system clock. That is, the output of the accumulator constitutes an accumulation of the FTW over time - hence its name.