Mastering ModelSim: A Comprehensive Guide to HDL Simulation

2023-08-11 | By DWARAKAN RAMANATHAN

License: General Public License

Introduction:

ModelSim, a powerful hardware description language (HDL) simulation software, revolutionizes the design and verification process for digital systems. From FPGA prototyping to ASIC development, ModelSim empowers engineers and designers to simulate, debug, and analyze complex digital designs with exceptional accuracy and efficiency. In this blog post, we'll explore the key features and benefits of ModelSim, shedding light on how it simplifies the hardware development workflow and accelerates time-to-market.

How to download:

To download ModelSim-Intel Software go to: ModelSim-Intel® FPGAs Standard Edition Software Version 20.1.1

This software is available for two operating systems: Linux and Windows. Download the one you prefer and start installing the software on your device.

After installing the software, open it and you will see a window similar to this:

Creating a project:

 To create a project, go to File>New>Project.

After clicking on the project, another window will open asking for the project name and location. In this case, please name it Half Adder because we will be working on verifying the half adder using ModelSim.

After that, click on Create New File. Here we will create two files: 

• A Verilog file containing the design of the half adder
• A Verilog file containing the testbench for the design

Note: Please name it as I did because the module name in the code must match the file name.

You will have added two files to your project that you can see in the workspace. Your icon may be different depending on the program you use to edit the text file; I am using Notepad++. You can use the default notepad on your device, or Notepad++ can be found here: https://notepad-plus-plus.org/downloads/

Now, Open the first file by double-clicking on it and typing the code (do the same for both files).

Code for Halfadder.v:

module Halfadder(a,b,sum,carry);

input wire a,b;

output wire sum,carry;

assign sum=a^b;

assign carry=a&b;

endmodule

Code for test_halfadder.v:

module test_halfadder();
reg a,b;
wire sum,carry;
integer i;

Halfadder DUT(a,b,sum,carry);

initial
begin
a = 1'b0;
b = 1'b0;
end

initial
begin
for(i=0;i<4;i=i+1)
begin
 {a,b}=i;
#10;
end
end

initial
$monitor("input is %b %b and sum = %b, caryy = %b",a,b,sum,carry);

initial #100 $finish();
endmodule

The above two codes are written using Verilog (Hardware Description Language).

You can learn Verilog here: Verilog Tutorial for Beginners (chipverify.com)

Now, to know if there are any errors before simulating the design, we must compile them. To do so, right-click anywhere on the workspace and click on Compile>Compile All.

You will see a green tick across your files if your code is error-free.

Time to Simulate:

First, you should know that for simulation, we are going to use the testbench and not the design file. The testbench is built for simulation purposes. To simulate the test file, go to Simulate>Start Simulation. A new window will open asking for you to choose the file. Go to Work> (choose the test file), and click on OK.

This is an interesting part of the software. There will be a change in the workspace. You will see many new windows opening containing the signals (Objects) and a separate window to see the waveform.

To see the waveform of particular signals (Objects), select them by holding shift and dragging them to the waveform window.

As you have brought your signals to the waveform window, the simulation is ready to begin. To begin the simulation, go to Simulate>Run>Run All. Select No on the "Are you sure you want to finish?" window.

With the simulation running, check the signals corresponding to signals a, b, Sum, and carry using the truth table below. If the values of your truth table match your simulation, the design file is verified using a testbench. We have added only one test case in this testbench, but you can have many test cases and verify the design more accurately.

To stop the simulation, go down to the transcript window and type “stop”.

Now you can quit the software but make sure that you play with the code and simulate it with different circuits so that you can learn about verification using ModelSim.

Conclusion:

ModelSim empowers engineers with its rich features for HDL simulation, debugging, coverage analysis, and design management. Fast-track design, improve quality and gain confidence in bringing projects to market swiftly.

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