Flip Flops

Results: 2
Packaging
BulkCut Tape (CT)Digi-Reel®Tape & Reel (TR)
Function
Set(Preset) and ResetStandard
Output Type
ComplementaryTri-State, Non-Inverted
Number of Elements
12
Number of Bits per Element
18
Clock Frequency
50 MHz60 MHz
Max Propagation Delay @ V, Max CL
28ns @ 6V, 50pF30ns @ 6V, 50pF
Current - Output High, Low
5.2mA, 5.2mA7.8mA, 7.8mA
Current - Quiescent (Iq)
4 µA8 µA
Supplier Device Package
14-SOIC20-SOIC
Package / Case
14-SOIC (0.154", 3.90mm Width)20-SOIC (0.295", 7.50mm Width)
Stocking Options
Environmental Options
Media
Marketplace Product
2Results

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Mfr Part #
Quantity Available
Price
Series
Package
Product Status
Function
Type
Output Type
Number of Elements
Number of Bits per Element
Clock Frequency
Max Propagation Delay @ V, Max CL
Trigger Type
Current - Output High, Low
Voltage - Supply
Current - Quiescent (Iq)
Input Capacitance
Operating Temperature
Mounting Type
Supplier Device Package
Package / Case
14-SOIC
CD74HC74M96
IC FF D-TYPE DUAL 1BIT 14SOIC
Texas Instruments
5,710
In Stock
3,493
Marketplace
1 : ¥4.42000
Cut Tape (CT)
2,500 : ¥1.25733
Tape & Reel (TR)
Tape & Reel (TR)
Cut Tape (CT)
Digi-Reel®
Bulk
Active
Set(Preset) and Reset
D-Type
Complementary
2
1
50 MHz
30ns @ 6V, 50pF
Positive Edge
5.2mA, 5.2mA
2V ~ 6V
4 µA
10 pF
-55°C ~ 125°C (TA)
Surface Mount
14-SOIC
14-SOIC (0.154", 3.90mm Width)
20-SOIC
CD74HC374M96
IC FF D-TYPE SNGL 8BIT 20SOIC
Texas Instruments
1,584
In Stock
24,507
Marketplace
1 : ¥6.38000
Cut Tape (CT)
2,000 : ¥2.45265
Tape & Reel (TR)
Tape & Reel (TR)
Cut Tape (CT)
Digi-Reel®
Bulk
Active
Standard
D-Type
Tri-State, Non-Inverted
1
8
60 MHz
28ns @ 6V, 50pF
Positive Edge
7.8mA, 7.8mA
2V ~ 6V
8 µA
10 pF
-55°C ~ 125°C (TA)
Surface Mount
20-SOIC
20-SOIC (0.295", 7.50mm Width)
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of 2

Flip Flops


Flip-flops are elementary digital memory devices capable of storing a single logic state or "bit" of information. They have at least two inputs; one or more to communicate the data to be stored and another to indicate the point in time to store it. Different flip-flop types such as D (delay), SR (Set-Reset), and JK respond differently to the signals presented to their inputs and can be used to implement different logical functions. They differ from latches in that they are edge sensitive devices, whose retained logic state changes only at the moment a valid clock signal is received.