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Z16FMC Motor Control Capabilities Slide 7

The Zilog/Littelfuse Z16FMC utilizes a ZNEO® CPU which offers a high level of performance and features in the FMC product family, and provides support for more complex motor applications. Some of the features are: pipelined architecture with fetch, decode, and execute; 16 MB of program memory address space for object code and data with 8‐ or 16‐bit data paths; 8-, 16-, and 32-bit ALU operations; a 24‐bit stack with overflow protection; direct any register-to–any register architecture which allows each memory address to function as an accumulator, improving execution time and decreasing the required program memory improves execution time and decreases the required program memory; and a new instruction set to improve execution efficiency for code developed using higher level programming languages, including “C”.

PTM Published on: 2011-05-25