SRL16E cannot only be used to build a FIFO, but can also be used to build low-cost delay lines, which are seen in many designs. This example shows a 5-cycle delay line. One way to build this would be to cascade five registers in CEs as shows at the bottom of the slide. The other way to do this would be to have a single lookup table implemented in an SRL16E mode and with the address pins polled at 0100. Instead of four registers, you now use one lookup table. The same logic can be extended to an 8-cycle delay line where instead of eight registers, you use a single lookup table or to a 16-cycle delay line where instead of sixteen registers you would use a single lookup table.