The lookup table in Spartan-3 architecture cannot only be used for logic or memory, but can also be used as a 16-bit shift register. This is a capability which is unique to the Spartan architecture amongst the low, low cost FPGAs available. In this example, a 4-input lookup table is configured at a 16-bit shift register with a flip-flop at the output. This is called the SRL16E mode. The bottom diagram shows conceptually what this looks like. It is similar to having 16 registers cascading.  The input to this particular structure goes to the "D" input and is written at location "0"; but, the output can be read from any location, depending on the values of the address pins A3 to A0. This structure is very useful when your designs are register-intensive. Also, this structure is very amenable towards building a FIFO.