The FMMU (Fieldbus Memory Management Unit) provides a way to map an address in the EtherCAT space to local (EtherCAT Slave) address space. There are registers in the slave that are programmed to create these mappings. TI’s solution can have up to 8 such mappings. Most other systems also have maximum 8 such mappings. The master configures the FMMUs. The Sync Manager ensures the slave and master are not concurrently trying to read/write data to same memory location in the slave address space. This is done using either mailboxes or using 3 buffers. Mailboxes have a ready/busy type flag to ensure other party accesses it when the first one is done accessing it. In buffer mode, there are three buffers and one buffer is always available if the two sides are each accessing another buffer and marking its buffer as full. Sync managers are also configured using dedicated registers in the EtherCAT slave. The EtherCAT master programs these sync managers after initialization. The timer is used to keep track of time in each slave. This can be adjusted by the distributed clock protocol. This is a protocol in EtherCAT to ensure that all devices in the network have same time. This is possible after the clocks in each such device is synchronized to a common reference. The synchronization itself is done through the distributed clock protocol as specified by EtherCAT. The EtherCAT slave can generate a signal/interrupt when a user configured value of time is reached in the local clock. So, this is a way to generate a highly accurate time triggered signal for internal or external uses. The EtherCAT slave controller can record current time when a particular event (say, a low to high transition) occurs on a input signal. This is to communicate various events via interrupt to the host. Some EtherCAT operations require bit-wise OR of the data received in EtherCAT frame with data in the slave memory before it is inserted in the outgoing frame. Customer 1/0 type output can be generated via memory mapped operations in the EtherCAT slave in PRUSS v2. Up to eight pins on SA can be used as digital input/output pins. This is subject to pin mux constraints.