This slide will show the simplicity of Concerto IPC. Before going into the details of the IPC drivers, note that at the most basic level, the application does not require any separate software drivers to communicate between processors. It can utilize the message RAM’s and shared SARAM blocks to pass data between processors at a fixed address known to both processors. The sending processor can then use the IPC flag registers to flag the receiving processor that the data is ready. Once the receiving processor has grabbed the data, it will then acknowledge the corresponding IPC flag to indicate that it is ready for more messages. For instance, examine the example shown here. First, the M3 writes a message to the C28 in MtoC MSG RAM. It then writes a 1 to the appropriate flag bit in the MTOCIPCSET register. This sets the MTOCIPCFLG, which also sets the MTOCIPCSTS register on the C28, letting the C28 know that a message is available. The C28 then sees that a bit in the MTOCIPCSTS register is set. It then continues on to read the message from the MtoC MSG RAM and then writes a 1 to the same bit in the MTOCIPCACK register to acknowledge that it has received the message. This subsequently clears the flag bit in MTOCIPCFLG and MTOCIPCSTS. After this, the M3 can send more messages using that particular flag bit.