This figure shows how the IPC drivers are implemented behind the scenes in the dual core system. These details are invisible to the user application code. Note that the buffers and indexes in purple store the M3 Put buffer (or C28 Get buffer) and indexes, while buffers and indexes in blue store the C28 Put buffer (or M3 Get buffer) and indexes. On the Concerto, the buffers and indexes are stored in the MtoC and CtoM Message RAM’s. The pointers which access and control the “Put” and “Get” circular buffers and their indexes are packaged in a tIpcController data structure stored in local memory on both the M3 and C28. When one processor (for this example the M3) wishes to perform an operation on the other processor (the C28), first, the M3 writes messages into its Put Buffer (which is equivalent to C28’s Get Buffer), increments the PutWriteIndex, and sets C28’s MtoC IPC interrupt flag. The C28 sees the IPC interrupt flag and subsequently reads the messages from the Get Buffer and increments the GetReadIndex. The C28 then proceeds to process the commands according to the message contents and then acknowledges the MtoC IPC interrupt flag. The M3 can also read and process messages that C28 writes to its Put Buffer (which is M3’s Get Buffer).