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Power-Slide4

BLE operates in a cyclic sleep scenario during a connected state. To wake up at the precise time in order to listen to pings from the central or master BLE device, a BLE peripheral or slave device relies on the accuracy of the 32.768kHz sleep clock, which is used at both ends of the link. Due to inherent inaccuracies of the master and slave sleep clocks, the peripheral device wakes up earlier to avoid missing the ping from the master. During this Early On time, referred to as deltaT in the diagram, power is consumed, causing a power penalty. This DeltaT is proportional to the configured sleep time plus the inaccuracy of the master and slave sleep clocks combined. The BLE standard calls out the Master side of the sleep clock accuracy (MasterSCA) in eight distinct ranges defined by an octal value (0 – 7), as shown in the table. For example, a Master sleep clock accuracy in the range 0 to 20ppm is configured as an octal value of 7. On the slave/peripheral side, the standard calls out the sleep clock accuracy (SlaveSCA) in the range 0 to 500 ppm. The Master and Slave negotiate the connection parameters which include the sleep time, the connection latency with the Slave determining the wake up time depending on the combined accuracies of the sleep clock on the Master and Slave ends.

PTM Published on: 2016-04-01