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FSDR-Slide18

The BD9G101G provides an enhanced integrated feature set. Switching frequency for these devices is fixed at 1.5MHz by using a precise wave oscillation circuit. Due to the internal switching oscillation circuit, no external components are needed. A soft start feature prevents inrush current during start-up of the chip with a frequency fold-back function. This is operated by an internal frequency clock that increases with the FB voltage. Soft start time is set for 4mS from starting up the EN pin. Once the internal FB voltage rises to 0.75V, 1.5MHz is held and the output voltage is enabled. The heat protection circuit activates when the maximum junction temperature exceeds 175°C. During this condition, the output FET is turned off. The output is turned on again once the temperature falls below 150°C. The Under Voltage Lock Out (UVLO) detector monitors the Vin pin voltage. If the Vin voltage becomes 5.4V or lower the UVLO turns off the output FET and resets the soft start circuit. The available SSOP6 package is the same as a standard 6-lead SOT-23 package.

PTM Published on: 2013-07-26