A PLL is a closed-loop feedback control system. It generates an output clock signal that is locked in phase and frequency with the input signal. The main building blocks of a PLL are shown in the block diagram on this slide. These consist of the Phase Frequency Detector or PFD, the Loop Filter or LF and the Voltage Controlled Oscillator or VCO. This tutorial will discuss the functionality of each of these functional blocks. There are also three important frequency dividers which can be part of a complete PLL. The Pre-divider, denoted by P is optional, its role is to divide down the input frequency to a value supported by the PFD. The output divider, denoted by N, is also optional, it is used to divide down the output frequency of the PLL to the desired output frequency. The Feedback Divider, denoted by M, is always present, it divides the output of the VCO to be equal to the input frequency of the PFD. PLLs have a start-up time that is typically in the millisecond range, that is the time PLLs take to lock to the correct frequency.