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In summary, a phase locked loop is a closed-loop feedback control system which generates an output clock signal locked in phase and frequency with the input signal. The main building blocks of a PLL are the phase frequency detector, the loop filter, and the voltage controlled oscillator. Three important frequency dividers; the pre-divider is used to divide the input frequency to a value supported by the PFD, the output divider is used to divide the output frequency of the PLL to the desired output frequency, and the feedback divider which divides the output of the VCO to be equal to the input frequency of the PFD. The pre-divider and the output divider are optional, the feedback divider is always present. Jitter is a very important performance parameter to consider when selecting timing devices, and is defined as the difference between the actual location of an edge and its ideal location. Knowing the jitter performance of timing devices makes it possible to predict clock timing margins.
