The differentiating features of the LS1046A are shown in this block diagram. The LS1046A uses a Quad Arm Cortex-A72 running at 1.8 GHz with 64 b DDR controller, 2 MB of L2 cache arranged in one cluster and no L3 cache. This arrangement reduces the average cache latency by 22% compared with products with multiple cores and L3 cache. Also worth noting are the Network interfaces with up to 2x 10 GbE, 3x 2.5 GbE and 8x 1 GbE, 8 lanes of SerDes for high performance PCIe Gen3 and the DPAA for packet processing offload and the SEC block for crypto processing.