The figure shows typical bus waveforms at the start of a communication. During the first 7 clock pulses, the master drives the SDA line with the ‘address’ of a specific slave device. On the 8th clock pulse it sets the SDA line ‘high’ to ‘read’ data from the other device, or ‘low’ to send (write) data. During its 9th clock pulse it releases the SDA line. If the other device is connected to the bus and has decoded and recognized its ‘address’, it will acknowledge by pulling the SDA line low.

So, let’s summarize the sequence of events that occur for communication on the I²C bus:

1) The master waits until it sees no activity on the I²C bus. It checks the SDA and SCL lines for logic high levels which means the bus is free.

2) The master sends the START bit which tells the other ICs to start listening to the bus to determine if they are being addressed.

3) The master then provides a clock signal over the CLOCK (SCL) wire. It will be used by all the ICs as the reference time to determine if each bit of DATA on the data SDA wire is correct (valid) and can be used. The data on the SDA line must be valid at the time the clock (SCL line) switches from a 'low' to a 'high' voltage.

4) The master sends a unique binary slave address in serial form with the Most Significant Bit (MSB) first.

5) Further, it signals (with one bit) whether it wants to SEND or RECEIVE data from the other chip and waits for the acknowledgment.

6) After the target IC (or the slave) acknowledges all is OK, data can be transferred.

7) The first IC sends or receives as many 8-bit words of data as it wants. After every 8-bit data word the sending IC expects the receiving IC to acknowledge the transfer is going OK.

8) When all the data is finished, the first chip must free-up the bus and it does this with the 'STOP‘ bit. It is just one bit of information transferred by toggling the SDA line when the SCL line is high.

The bus rules specify that when data or addresses are being sent, the DATA wire is only allowed to be changed in voltage (so, '1', to '0') when the voltage on the clock line is LOW.

The 'start' and 'stop' special messages break this rule and this is how they are recognized as special.

Now, what if the slave is busy when the master is communicating? This situation is addressed by a feature called CLOCK STRETCHING. The diagram here shows that in pink. Clock stretching means that the slave will hold the clock line LOW to finish what it was doing before accepting more data from the master.