The top figure shows the hardware configuration of the I²C bus. The ‘bus’ wires are named SDA (serial data) and SCL (serial clock). These two bus wires have the same configuration. They are pulled-up to the logic ‘high’ level by resistors connected to a single positive supply, usually +3.3 V or +5 V but designers are now moving to +2.5 V and 1.8 V in the near future. All of the connected devices have open-collector (open-drain for CMOS) driver stages that can transmit data by pulling the bus low, and high impedance sense amplifiers that monitor the bus voltage to receive data. If the devices are not communicating, both bus lines remain ‘high’. To initiate communication a chip pulls the SDA line low. It then has the responsibility to drive the SCL line with clock pulses, until it has finished, and this is called the bus ‘master’. The bottom figure shows that multiple masters and slaves can be on the same bus. Bi-directional communication is possible without any data collision. For reference, some common terms associated with the I²C bus protocol are provided in the page notes below.

Transmitter - the device that sends data to the bus. A transmitter can either be a device which puts data on the bus to request something from another device (a ‘master-transmitter’), or puts data as a response to a request from another device (a ‘slave-transmitter’).

Receiver - the device that receives data on the bus from the transmitter.

Master - the component that initializes a transfer, generates the clock signal, and terminates the transfer. A master can be either a transmitter or a receiver.

Slave - the device addressed by the master. A slave can be either a receiver or transmitter.

Multi-master - the ability for more than one master to co-exist on the bus at the same time without collision or data loss.

SDA – is an acronym for Serial Data and is the data signal line.

SCL - is an acronym for Serial Clock and is the clock signal line.