As mentioned earlier, the PIC24F provides a natural migration path up from the PIC18. First, the PIC24F provides increased memory. On the first family we expand the RAM to 8kB and the Flash to 256kB. It would be a fair guess that the 256kB Flash on the first family will not be the limit for too long. Along with the increased memory is of course increased performance, with a 16-bit MCU operating at 16 MIPS. In addition to the natural core performance, there have been several improvements to the peripheral set. The device contains five 16-bit timers, four of which can be cascaded to form two 32-bit timers. There is also a new high speed 10-bit ADC. The 10-bit ADC is capable of conversion rates of up to 500K samples per second. JTAG Boundary Scan has been added to the PIC24F family to assist in board level testing and in system programming. The PIC24F also includes multiple independent I²C™, UART and SPI ports. The UART functionality has been upgraded to include IrDA® functionality. Both the UART and SPI have been enhanced to include built in FIFO. The FIFOs are included in the serial port to reduce the number of times the processor must service the peripheral, reducing the overhead required to service the peripherals. The Parallel Slave Port contained on the many PIC18 devices has been replaced by a Parallel Master Port. Similar to the PIC18, the PMP allows the PIC24F to address or be addressed as a parallel device, and perhaps more important, the PMP allows the PIC24F to use an external memory for data storage.