Microchip's PIC24F core beats most of the 16-bit competitors and provides a real migration path for our 8-bit PIC18 Families. When operating off a 32MHz clock the performance is roughly ½ of the clock rate, or equivalent to instruction execution time. In addition to faster execution time and a 16-bit data bus there are several other additions to the core. First, the interrupt structure of the PIC24F family is significantly upgraded. The PIC24F provides an independent interrupt vector for each interrupt source. Interrupt priorities can be set at any of 16 levels. The PIC24F family provides 16 working registers. The PIC24F implements 16-bit math, including a 17 X 17 single cycle multiply. The architecture also implements a single cycle multiple bit shifter, or barrel shifter. The instruction set and addressing modes work to improve the PIC24F C code efficiency. Finally, the PIC24F core incorporates a “repeat” instruction. This instruction allows a math instruction, or a memory transfer instruction to be repeated a specified number of times. For example, the repeat can be used to transfer a block of data with one word being transferred per instruction cycle.