This slide will take a closer look at some of the LTC2978’s supply functions to give customers a better idea on the capabilities of this sophisticated IC. Shown here is an example of sequencing up, margining and then sequencing down. Certain processors require that their I/O voltage rise before their core voltage whereas certain DSPs require their core voltage to rise before their I/O. Power down sequencing is also now required. An ideal sequencer would allow arbitrary sequencing of any rail in the system and allow any rail to depend on any other rail. This is accomplished on the LTC2978 by using one universal clock to synchronize all ICs to the same time base. Since sequencing delays are typically at the millisecond level, this clock can be low frequency, and low noise. The Share clock input on the LTC2978 operates on a 100kHz clock. In a cascaded configuration, none of LTC2978s will start their sequencing activities until the last one lets go of the share clock line and it starts oscillating at nominally 100kHz; this assures that all LTC2978s have successfully loaded EEPROM to RAM and that each one sees an input voltage on the intermediate bus greater than the specified input voltage (V_IN_ON) at which the unit should start power conversion. This ensures that an array of LTC2978s will not power a multi-rail system until they all agree that the bus is ready. In a multi-rail sequencer, most dependencies are established with configurable settings within the sequencer. If there is a need to establish dependencies across sequencers, a fault-sharing bus can be used between sequencers. A fault group may be the core and I/O rail of one processor or all 7 rails on an ASIC. A dependency is established between these rails, such that if one of them does not come up to its full voltage during the power-up sequence, the sequence is aborted.