For a high stress staged start, the stress MOSFET, Q1, is selected for actively limiting inrush current and for riding through load surges and input voltage steps with a longer fault timer. The R_DS(ON) MOSFET, Q2, is kept off during stressful events with GPIO2 configured as a stress signal, which depends on large drain-to-source voltage and gate-to-source not being completely on. For comparison, this configuration will have half the stress handling capability of the matched configuration if the stress MOSFET is similar to that in one of the matched paths.