Over time, as DRAM technology evolves, experts like to understand the effect to the cause and prevalence of errors. Papers have pointed out a couple findings: the first is that Variable Retention Timing (VRT) errors can increase as geometries get smaller. The DRAM memory cell is retained due to the charge of a capacitor, and smaller geometry capacitors generally hold lower level charges than those in previous generations. Also, transistors may have more chance of being leaky, so the charge can dissipate faster. In-DRAM ECC helps repair bits that have failed due to these reasons, and helps result in increased field reliability. The second paper, much earlier, found that the integrity of circuits would be more vulnerable to errors as the geometry shrinks because of lower voltages and higher frequencies. ECC also helps reduce these transient and intermittent errors.