The MxL7704-A factory configurations are optimized for 64- and 32-bit Arm Cortex A53, A7 and A9 processors. Output voltages are preset to: 3.3 V for the LDO, 3.3 V for Analog and I/O rails, 1.8 V for additional I/O, 1.35 V for DDR3L memory, and 1.2 V for the core rail. Sequencing is set for I/O first, core last, so the LDO powers up first; followed by SEQ_EN; 3.3 V; 1.8 V, and the 1.35 V and 1.2 V rails power up last. PGOOD1 is assigned to Buck 2 or 1.8 V and PGOOD2 is assigned to Bucks 3 and 4 or 1.35 V and 1.2 V. The switching frequency is set to 1.5 MHz. The MxL7704 offers a register that allows the user to choose whether a fault on a given channel will only affect that channel or cause an entire restart of the power system. The MxL7704-A is pre-configured with this register set for “chip” fault. This means a fault on any channel will cause the other channels to simultaneously power down based on their power down settings. Once all channels are powered down, a 1 ms delay will gate the restart of the channel or chip and soft off is enabled.