Flip Flops

Results: 4
Function
Set(Preset) and ResetStandard
Output Type
ComplementaryTri-State, Non-Inverted
Number of Elements
12
Number of Bits per Element
18
Clock Frequency
130 MHz140 MHz
Max Propagation Delay @ V, Max CL
8.8ns @ 5V, 50pF10.4ns @ 5V, 50pF
Current - Quiescent (Iq)
2 µA4 µA
Supplier Device Package
14-TSSOP20-TSSOP
Package / Case
14-TSSOP (0.173", 4.40mm Width)20-TSSOP (0.173", 4.40mm Width)
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Mfr Part #
Quantity Available
Price
Series
Package
Product Status
Function
Type
Output Type
Number of Elements
Number of Bits per Element
Clock Frequency
Max Propagation Delay @ V, Max CL
Trigger Type
Current - Output High, Low
Voltage - Supply
Current - Quiescent (Iq)
Input Capacitance
Operating Temperature
Grade
Qualification
Mounting Type
Supplier Device Package
Package / Case
0
In Stock
Obsolete
Tape & Reel (TR)
Obsolete
Standard
D-Type
Tri-State, Non-Inverted
1
8
130 MHz
10.4ns @ 5V, 50pF
Positive Edge
8mA, 8mA
4.5V ~ 5.5V
4 µA
4 pF
-40°C ~ 85°C (TA)
-
-
Surface Mount
20-TSSOP
20-TSSOP (0.173", 4.40mm Width)
0
In Stock
Obsolete
Tape & Reel (TR)
Obsolete
Standard
D-Type
Tri-State, Non-Inverted
1
8
130 MHz
10.4ns @ 5V, 50pF
Positive Edge
8mA, 8mA
4.5V ~ 5.5V
4 µA
4 pF
-40°C ~ 85°C (TA)
-
-
Surface Mount
20-TSSOP
20-TSSOP (0.173", 4.40mm Width)
0
In Stock
Obsolete
Tape & Reel (TR)
Obsolete
Set(Preset) and Reset
D-Type
Complementary
2
1
140 MHz
8.8ns @ 5V, 50pF
Positive Edge
8mA, 8mA
4.5V ~ 5.5V
2 µA
4 pF
-40°C ~ 85°C (TA)
-
-
Surface Mount
14-TSSOP
14-TSSOP (0.173", 4.40mm Width)
0
In Stock
Obsolete
Tape & Reel (TR)
Obsolete
Standard
D-Type
Tri-State, Non-Inverted
1
8
130 MHz
10.4ns @ 5V, 50pF
Positive Edge
8mA, 8mA
4.5V ~ 5.5V
4 µA
4 pF
-40°C ~ 85°C (TA)
-
-
Surface Mount
20-TSSOP
20-TSSOP (0.173", 4.40mm Width)
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of 4

Flip Flops


Flip-flops are elementary digital memory devices capable of storing a single logic state or "bit" of information. They have at least two inputs; one or more to communicate the data to be stored and another to indicate the point in time to store it. Different flip-flop types such as D (delay), SR (Set-Reset), and JK respond differently to the signals presented to their inputs and can be used to implement different logical functions. They differ from latches in that they are edge sensitive devices, whose retained logic state changes only at the moment a valid clock signal is received.