Flip Flops

Results: 2
Manufacturer
onsemiTexas Instruments
Series
17SZ74AUP
Packaging
Cut Tape (CT)Digi-Reel®Tape & Reel (TR)
Product Status
ActiveObsolete
Clock Frequency
100 MHz200 MHz
Max Propagation Delay @ V, Max CL
5ns @ 5V, 50pF7ns @ 3.3V, 30pF
Current - Output High, Low
4mA, 4mA32mA, 32mA
Voltage - Supply
0.8V ~ 3.6V1.65V ~ 5.5V
Current - Quiescent (Iq)
500 nA1 µA
Input Capacitance
1.5 pF7 pF
Operating Temperature
-55°C ~ 125°C (TA)-40°C ~ 85°C (TA)
Supplier Device Package
8-VSSOPUS8
Stocking Options
Environmental Options
Media
Marketplace Product
2Results

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of 2
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Mfr Part #
Quantity Available
Price
Series
Package
Product Status
Function
Type
Output Type
Number of Elements
Number of Bits per Element
Clock Frequency
Max Propagation Delay @ V, Max CL
Trigger Type
Current - Output High, Low
Voltage - Supply
Current - Quiescent (Iq)
Input Capacitance
Operating Temperature
Grade
Qualification
Mounting Type
Supplier Device Package
Package / Case
8-TSSOP, 8-MSOP
SN74AUP1G74DCUR
IC FF D-TYPE SNGL 1BIT 8VSSOP
Texas Instruments
32,012
In Stock
1 : ¥3.49000
Cut Tape (CT)
3,000 : ¥1.40270
Tape & Reel (TR)
Tape & Reel (TR)
Cut Tape (CT)
Digi-Reel®
Active
Set(Preset) and Reset
D-Type
Complementary
1
1
100 MHz
7ns @ 3.3V, 30pF
Positive Edge
4mA, 4mA
0.8V ~ 3.6V
500 nA
1.5 pF
-40°C ~ 85°C (TA)
-
-
Surface Mount
8-VSSOP
8-VFSOP (0.091", 2.30mm Width)
8 VFSOP
NLV17SZ74USG
IC FF D-TYPE SNGL 1BIT US8
onsemi
0
In Stock
1 : ¥5.09000
Cut Tape (CT)
3,000 : ¥1.84701
Tape & Reel (TR)
Tape & Reel (TR)
Cut Tape (CT)
Digi-Reel®
Obsolete
Set(Preset) and Reset
D-Type
Complementary
1
1
200 MHz
5ns @ 5V, 50pF
Positive Edge
32mA, 32mA
1.65V ~ 5.5V
1 µA
7 pF
-55°C ~ 125°C (TA)
Automotive
AEC-Q100
Surface Mount
US8
8-VFSOP (0.091", 2.30mm Width)
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Flip Flops


Flip-flops are elementary digital memory devices capable of storing a single logic state or "bit" of information. They have at least two inputs; one or more to communicate the data to be stored and another to indicate the point in time to store it. Different flip-flop types such as D (delay), SR (Set-Reset), and JK respond differently to the signals presented to their inputs and can be used to implement different logical functions. They differ from latches in that they are edge sensitive devices, whose retained logic state changes only at the moment a valid clock signal is received.