Flip Flops

Results: 2
Packaging
BulkTube
Function
Set(Preset) and ResetStandard
Output Type
ComplementaryTri-State, Non-Inverted
Number of Elements
12
Number of Bits per Element
18
Clock Frequency
33 MHz50 MHz
Max Propagation Delay @ V, Max CL
28ns @ 5V, 45pF40ns @ 5V, 15pF
Current - Output High, Low
400µA, 8mA2.6mA, 24mA
Current - Quiescent (Iq)
8 mA40 mA
Supplier Device Package
14-SOIC20-SOIC
Package / Case
14-SOIC (0.154", 3.90mm Width)20-SOIC (0.295", 7.50mm Width)
Stocking Options
Environmental Options
Media
Marketplace Product
2Results

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Mfr Part #
Quantity Available
Price
Series
Package
Product Status
Function
Type
Output Type
Number of Elements
Number of Bits per Element
Clock Frequency
Max Propagation Delay @ V, Max CL
Trigger Type
Current - Output High, Low
Voltage - Supply
Current - Quiescent (Iq)
Operating Temperature
Mounting Type
Supplier Device Package
Package / Case
14-SOIC
SN74LS74AD
IC FF D-TYPE DUAL 1BIT 14SOIC
Texas Instruments
0
In Stock
3,645
Marketplace
750 : ¥5.77504
Tube
Bulk
Tube
Obsolete
Set(Preset) and Reset
D-Type
Complementary
2
1
33 MHz
40ns @ 5V, 15pF
Positive Edge
400µA, 8mA
4.75V ~ 5.25V
8 mA
0°C ~ 70°C (TA)
Surface Mount
14-SOIC
14-SOIC (0.154", 3.90mm Width)
20-SOIC,DW
SN74LS374DW
IC FF D-TYPE SNGL 8BIT 20SOIC
Texas Instruments
729
In Stock
5,945
Marketplace
1 : ¥9.69000
Tube
Bulk
Tube
Obsolete
Standard
D-Type
Tri-State, Non-Inverted
1
8
50 MHz
28ns @ 5V, 45pF
Positive Edge
2.6mA, 24mA
4.75V ~ 5.25V
40 mA
0°C ~ 70°C (TA)
Surface Mount
20-SOIC
20-SOIC (0.295", 7.50mm Width)
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Flip Flops


Flip-flops are elementary digital memory devices capable of storing a single logic state or "bit" of information. They have at least two inputs; one or more to communicate the data to be stored and another to indicate the point in time to store it. Different flip-flop types such as D (delay), SR (Set-Reset), and JK respond differently to the signals presented to their inputs and can be used to implement different logical functions. They differ from latches in that they are edge sensitive devices, whose retained logic state changes only at the moment a valid clock signal is received.