A more pictorial way of representing the information form the last slide is shown here. This diagram shows three different threads running in a system. The highest priority thread is the hardware interrupt which is running periodically to collect some kind of sample. After the Hwi collects nine samples, it posts a software interrupt, which the scheduler initiates as soon as the higher priority Hwi has completed. The Swi can then begin processing the set of samples; however, it will be immediately preempted the next time the Hwi is ready to run. When the Swi resumes, it can then finish running to completion. Since neither the Swi or the Hwi are running at that point, the scheduler will run the lowest priority idle thread. The advantage of this arrangement should now be clear. The amount of time that spent processing hardware interrupts in the Hwi has been minimized because the processing of the buffer of data is deferred to a lower priority thread. The system will ultimately be more reliable because the window in which the interrupts need to be disabled is narrowed. Additionally, the software design will be more modular since the buffer processing is all within a separate function. The system is also more extensible due to the fact that if additional types of processing need to be added later on, they can be introduced into additional threads that are appropriately prioritized.