Flash endurance is affected by writes to the NAND cell.  The threshold voltage level shifts as the NAND cell ages.  Each write and erase process damages the floating gate.  The key factor in the design differences between MLC and SLC NAND Flash is the controlling write and read circuitry for all cell locations.  Because of the increased Vt range for valid states between a 0 and 1 for SLC operation, the endurance and data retention increases significantly.  Specifically, this occurs as follows: A voltage difference between the drain and the source, Vd – Vs, creates an electric field between the drain and the source.  This electric field converts the previously nonconductive poly-Si material to a conductive channel, which allows electrons to flow between the source and the drain.An electric field caused by a large gate voltage, Vg, is used to pull electrons up from this conductive channel onto the floating gate.  This gate voltage gives the electron enough energy to be pulled onto the floating gate.  The number of electrons on the floating gate affects the threshold voltage of the cell Vt.  This effect is measured to determine the state of the cell.  Over time the floating gate retains more and more residual electrons which will shift the threshold voltage higher.  As this Vt becomes higher the proper level detect range also becomes smaller.  With SLC the threshold level shift is not as critical and leaves more margin, thus SLC NAND has better endurance reaching about~100k PE cycles.  With MLC the level shifts across the threshold earlier, making the endurance of MLC NAND much shorter, about 1k PE cycles.