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The STM8 core delivers 20 MIPs performance at 24 MHZ using an advanced Harvard and CISC (complex instruction set computer) architecture. New arithmetic instructions increase computational performance with faster multiply and divide operations. 128 KB linear address space means no need for paging. The 3-stage pipeline allows operations to happen in parallel, which combined with the 32-bit internal memory interface, increases efficiency and improves performance. The advanced clock controllers allow the core to quickly move between high speed clocks when performance is needed and low speed clocks for power efficiency.
PTM Published on: 2011-12-14
