As mentioned earlier, the PCA is responsible for capturing the timing events for the PRX going low and again when it goes high. In this application the PCA is also responsible for setting the STX time base for initiating measurements in which the fastest rate recommended for the Si1120 is 500 Hz. In this example, the rate has been set to 400 Hz. With that in mind, the clock source has been set to the PCA; and it is assumed there is a system clock of 24.5 MHz which is very common among Silicon Labs devices. If the 16 bit counter were to be used without scaling the clock input, a minimum overflow rate of 387 Hz (24.5 MHz/65536) could be achieved. This hits the target of 400 Hz, however, it does not leave a lot of room to modify the system level performance, for example, if it was desired to run below 100 Hz to reduce power. The flip side is the desire to provide as much resolution for the measurement as possible. A frequency of 96 Hz and a resolution of 160 ns can be provided by using the SYSCLK/4 as the counter input. After setting the clock, the PCA channels are then configured. Channel 1 is set to drive the STX output for the 400 Hz output and channel 0 is set to measure the PRX output. There is a section in the code that sets the PCA0CPL1/CPH1 registers and adds a divide ratio. This allows a constant frequency output from the PCA module similar to the hardware functionality of some other timers in the C8051F family.