As mentioned previously, in synchronous serial communications, the transmitter sends the data out the pin at a specific rate determined by the internal clock system. This clock is also output along with the data in order for a receiving device to know when to latch the incoming data bits. By sending the clock output along with the data, there are no additional bits required to provide a synchronization time for a receiver. The receiving device just latches the data based on the received clock and converts the data internally to a parallel value for use by the CPU. Clock speed, clock polarity and data width are all established at design time. One aspect not shown here is the use of a chip enable (CE) control signal. In some synchronous serial interfaces, the chip enable is used to allow multiple devices to be connected to the same bus. This is typical of Serial Peripheral Interface (SPI) devices.