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Inst Arch

This presentation will begin with an understanding of the Cortex-M0 instruction set. The Cortex-M0 is a RISC or Reduced Instruction Set Computer architecture based on the ARM thumb concept. The complete instruction set for the Cortex-M0 can be seen in this diagram. Almost all of the Cortex-M0 instructions are 16-bits in length but operate on 32-bit registers and 32-bit data paths. The only 32-bit instruction used in application code is the B-L or Branch with Link instruction.

PTM Published on: 2011-03-10