Reviewing the important parameters of the ESD diode and the relationship to the IC that its trying to protect, illustrated is a typical textbook IV curve of an ESD diode. The reverse region is the area of interest as the typical topology is that of the ESD diode is connected to ground on the anode side. As voltage and current increase in the reversed bias direction, the voltage-current relationship will be plotted as shown accordingly. There are 5 major parameters to consider. The first parameter in the ESD diode datasheet is the maximum reverse working voltage. This is the operational voltage of the signal to be protected. For example, USB1.1 signals are 5 V, so therefore, the VRWM choice is 5 V. The breakdown or VBR parameter is basically when the curve is entering the on-region or when the avalanche occurs at 1 mA. The clamping voltage is any voltage during the on-region with respect to its peak pulse current. In the ESD diode datasheet, there should be two clamping voltages specified along with their respective peak pulse currents. The clamping voltage may either be specified using a 8 microsecond rise and 20 microsecond delay time waveform in order to generate the clamping voltages at 1 A and 3 A, for example; or use a TLP pulse (typically 100 ns) to get the clamping voltages at 16 A and 30 A. Once there are two data points, then the calculation of the slope results in the dynamic resistance. The diode’s resistance is probably the most important parameter which dictates the clamping voltage. Low dynamic resistance results in a low clamping voltage, which in turn results in less residual energy into the IC. The ESD destruction voltage is the point in which the junction or ESD diode has reached its maximum protection capability, whether it is a process limitation or a thermal breakdown due to the energy passing through it causing the junction temperature increase. For signal integrity considerations, the junction or line capacitance is important for high speed or RF signals. Every diode has an inherent parasitic capacitance which limits the slew rate and hence the integrity of the high speed signal. It will be discussed what capacitances are suitable for what type of applications and data rates further in this presentation.