Shown on this slide is the block diagram of the XR20M1280 device. This UART has a user selectable I²C or SPI interface. It can operate from 1.62V to 3.63V.  The VCC voltage levels for the CPU bus interface, UART I/Os, GPIOs and the core can all be at the same or different levels within this range. Depending on the package, there are different options for the number of GPIO pins available on the device. The XR20M1280 can support up to sixteen GPIO pins. In addition, there is a 128-byte transmit FIFO and a 128-byte receive FIFO. The on-chip fractional baud rate generator or FBRG helps in reducing external component count.