Shown here is a block diagram of the XR17V35x. The PCIe UARTs have anywhere from two to eight UART channels with 256-Byte transmit and receive FIFOs on chip. The PCIe PHY and endpoint controller is integrated as well. A SPI interface is provided, which allows for an external EEPROM to be connected. The customer can program their own PCI Vendor ID and Device ID into this external memory. The on-chip buck regulator ensures minimum power consumption for the device. There are up to sixteen general purpose I/O pins and an optional expansion port interface on the four and eight channel devices. This expansion port can enable up to sixteen UART channels to be connected to a single one lane PCIe host interface.