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Challenges Addressed by CoreHC

While characterizing and validating the SoCs, FPGAs and CPU ICs with large pin count packages like BGA type, the challenge is to get as close as possible to high frequency pins for probing. Another challenge is to keep the trace between pin and probing pad as short as possible so that the high frequency losses can be minimized. CoreHC™ provides an excellent solution with phase matching down to 2 ps between the signal pairs for both Co-planer and Stripline type PCB lay outs. With high performance coaxial cables and RF shielding of greater than 100 dB, cross talk is kept to a minimum.

PTM Published on: 2022-05-10