The SAM4S series integrates Flash read accelerator along with cache memory to increase system performance. The 2 KB of cache allows the execution of the code without any penalty coming from the wait state. The code is seemingly executed at 0 wait state. The maximum CoreMark achieved by this architecture is 3.38 CoreMark/MHz. As the SAM4S can run at 120 MHz, the maximum performance is 408 CoreMark. The microcontroller series integrates a Flash read accelerator along with cache memory to increase system performance. Additional key specs include a multi-layer bus matrix, multi-channel direct memory access, and distributed memory to facilitate high data rate communication.