An ideal DAC would transition from one level to another instantly and accurately. A real-world DAC, however, will not follow this ideal. When a new code is loaded, there is a delay before the output starts to change. Furthermore, the output will take time to transition to its new level; this is dependent on the slew rate. Finally, the output might not stop at the final value right  away – it may overshoot and oscillate before settling (note that this can be load dependent). Settling time is the measure of how long it takes for the output to settle to plus or minus 0.5 LSBs of the final value from the time it was programmed to update. This can be referenced from the last clock edge or a rising edge of /CS, for example. The final settled output value will be within the total unadjusted error specifications for the part.