With a leading edge of 20 nm a datapath solution, like Intel®’s Arria® 10 FPGAs, have multiple power rails, at different voltage levels, each with specific tolerances and sequencing requirements. Shown here is the power up and monitoring of a typical Arria® 10 FPGA design using Intel® Enpirion® power modules and a MAX® 10 FPGA as the system manager. The MAX® 10 FPGAs contain one or two integrated 12 bit successive approximation register (SAR) ADCs. There are 16 analog inputs multiplexed to the ADCs enabling the MAX® 10 FPGA to monitor a large number of analog signals. A MAX® 10 FPGA configures in just a few milliseconds (<5ms), making it an instant-on device in the context of system management. This enables the MAX® 10 FPGA to configure, control, and initialize the rest of the board. Using an analog input, the MAX® 10 FPGA will monitor the line side of the primary power rail (A0) and if within operating tolerances, power-on state, enter the power-up stage. Turning on the Enpirion PowerSoCs using digital logic and general-purpose I/O (GPIO) (D1 – D6) in a controller manner, the MAX® 10 device ensures the Arria® 10 devices powers up correctly. By monitoring the load side of the power, the MAX® 10 devices ensure that each rail is operating at the correct level (A0 – A6), and then it can release the Arria® 10 FPGA from reset for normal operation. The MAX® 10 FPGA, with up to 16 analog inputs, has sufficient analog resources to monitor the multiple voltage rails for the Arria® 10 FPGA. After the Arria® 10 FPGA is released from reset and is operating, the MAX® 10 FPGA can continue to monitor the system power rails. A faulty power supply is not always easy to diagnose from a system level. If a power rail ‘dips’ out of tolerance, it can put the device, or parts of the device into an unknown state. In reality, this means device operation cannot be guaranteed. The portions of the device may continue to operate correctly, but other parts may not. So it is important for the system manager to stay vigilant in monitoring the power rails and if there is a deviation, it can reinitialize the system as needed. The MAX® 10 FPGAs can sample a power once every half microsecond. This means each power rail can check every few microseconds, depending upon how many power rails are being monitored. The increase in power consumption of these datapath FPGAs, ASSPs, and CPUs has an increasing impact in a number of areas, including local thermal management, cost of operation, and facility-wide cooling requirements. To help offset facility cooling, it can be advantageous to power down some or all of the board FPGAs during times of reduced work load. In the example on this slide, Intel® shows a single Arria® 10 FPGA, but in systems where multiple Arria® 10 FPGAs are employed, the MAX® 10 FPGA can control them independently and power one or more of them as application needs dictate. These high-powered devices often have specific power-down sequence to ensure long term reliability of the device. Just as the MAX® 10 FPGA initialized the system at startup, it has the right mix of analog and digital resources to power down the PowerSoCs in the required sequence to power down the system in a safe and controlled manner.