Power Strategy for Optical Infrastructure

Optical communications switches form the backbone of the modern telecommunication and data-communication infrastructure. Over the past couple of decades they have seen dramatic changes in architecture as they have become increasingly powerful.

They combine high-performance optical control with parallel digital processing based on the most advanced semiconductor processes available. As a result, the systems require a large number of power domains, many of them providing a combination of high current and low voltage. To fit into the modern communications hub, the power systems need to be highly efficient. As voltages have reduced, the demand for efficiency has forced changes in the way that energy is delivered to each processor and optical transceiver module.

Originally, telecommunication systems employed a centralized power architecture, with AC being converted to −48 V_DC by a front-end rectifier feeding a set of DC/DC converters. High-current bus bars routed the required voltages to each shelf inside the cabinet, which contained the line cards used for switching. The bus bars were not just bulky, they were expensive and made it harder to perform regulation of the supply.

In the 1990s, the power-delivery architecture used by many telecom systems changed to a distributed power architecture in which the 48 V supply was delivered to a larger number of DC/DC converters sited locally to the line cards and other compute elements. The trend was driven by a gradual lowering in voltages and increases in current, as well as more control over power sequencing to allow hot-swapping of modules.

The distributed-power architecture was devised on the assumption there would typically be just one, or maybe two, different load voltages per board. For most 48 V systems, providing isolation between the higher distribution voltage and the target-voltage is a requirement. Isolated converters tend to be larger and more expensive than their non-isolated equivalents. The isolation stage calls for a transformer whereas most non-isolated designs can simply use an inductor. Also, the PCB design of the converter is more complex, as isolation barriers are needed between the control signals that pass between the primary and secondary side that the converter circuitry needs to provide accurate control.

However, even the distributed-power architecture limits flexibility in terms of the number of rails that can be supported. Providing for more than two output voltages with isolated converters requires significant amounts of space and rapidly becomes expensive. The high-density field-programmable gate arrays (FPGAs) and processors used in optical-networking systems often have complex power requirements, involving a large number of low-voltage supply rails. For example, the serial transceivers used on high-density FPGAs will have different requirements to those used for the core fabric, which may be different from those used for general-purpose I/O.

One way to deal with the problem is to use cascaded power converters, using a 48 V-to-5 V module feeding a set of non-isolated buck regulators and low-dropout regulators (LDOs) that generate the required voltages. This approach has become formalized through the adoption of an intermediate bus architecture (IBA), which allows the use of voltage rails that are better tuned for overall efficiency.

The IBA introduces a further layer of DC/DC converters that can be placed close to each load. In many systems, the IBA-based power system includes a front-end AC/DC power supply with a typical output of 24 V or –48 V. This voltage is supplied to an intermediate bus converter that provides isolation and conversion to a lower-level intermediate-bus voltage, typically in the 5 V to 14 V range. The 12 V rail is a common choice. This intermediate-bus voltage is supplied to non-isolated, point-of-load (POL) regulators that provide high-quality voltages for a variety of digital and analog electronic blocks that operate from voltages from 0.5 to 5 V.

System cost is reduced with the IBA because it reduces the number of isolated DC/DC converters that are needed; removing the need for isolation reduces the complexity and cost of POL regulators. Conversely, because the POL regulators deliver precise regulated voltages to the target devices, the regulation constraint on the intermediate bus converter can be significantly lower. As the POL regulators are mounted very close to the target devices, the quality of regulation is higher and reduces the losses associated with delivering high currents at low voltage. The intermediate converters can also often tolerate modest variations coming from the AC/DC supply to their DC inputs, which can lead to possible cost savings in the front-end rectifier.

Older power-supply designs tend to offer the greatest efficiency at peak power. However, this does not reflect the normal use of many networking systems. Most will have variable levels of activity and will also have their power systems specified to cope with high peak levels, but will spend much of their time running below full load. Furthermore, the use of N+1 topologies to provide redundancy means that the power converters will only run close to peak level if one of the converters has failed. As a result, intermediate bus converters are being designed to offer better efficiency at lower loads, often down to a third or quarter of the maximum output.

CUI’s NQB-D and NQB-N families of fully regulated intermediate bus converters provide efficiency of 96.4% at half load. The converters each use an industry-standard quarter-brick form factor to provide a power density of up to 140 W per square inch. The converters have input-to-output isolation of up to 2250 V_DC.

GE Critical Power’s Barracuda series of DC/DC converters were designed to support intermediate bus architectures, offering full regulation over their 12 V_DC outputs. As an example, the QBVW033A0B operates from an input-voltage range of 36 to 75 V_DC and provide up to 33 A output current. It uses a standard quarter-brick form factor and uses synchronous rectification to help achieve efficiency exceeding 96%, even at one-third of maximum current. Novel packaging and design efficiency allows the supply to be used without a heatsink in many applications.

Designed to offer stability without output capacitors on low-inductance power buses, the Power-One QME48T20120 delivers up to 20 A at 12 V from a 48 V input. Packaged as a quarter-brick unit, it offers up to 2 kV isolation and can be used without heatsinks to reduce its impact on the system’s airflow. Its design delivers 95% efficiency from a quarter of full load to a half. Another possibility is TDK Lambda’s Asceta iQG power module. This is also based on a quarter-brick form factor, offers up to 96% efficiency, and can deliver up to 33 A.

The shift to IBA has provided the opportunity to innovate on power-conversion circuitry. Depending on the input-voltage range and the electronic system’s requirements for voltage, there are other possible choices for the intermediate-bus voltage than 12 V_DC. Of course, there are potential tradeoffs over the decision on where best to provide good voltage regulation.

The continuing drop in voltage levels in processor and memory subsystems drove Vicor’s introduction of the factorized-power architecture. It uses a different approach to the intermediate bus architecture that takes advantage of reducing the amount of regulation on the intermediate bus itself.

The factorized-power system is designed to maximize efficiency under light-load conditions and maintain that efficiency through to peak conditions. Using this strategy, bus converter modules replace the 12 V-output bricks. Although some models provide a 12 V output, they are available with output voltages up to 48 V, to take advantage of reduced losses, and operate from a 380 V_DC input. The modules are designed to operate in parallel using a mechanism akin to phase shedding in multiphase power converters. Under light-load conditions, one or more of the bus converter modules will shut down rather than operate at low efficiency.

To provide the ability to step down from 48 V to 1 V or below to power leading-edge processors and FPGAs, the POL converter has been split into two parts. The name ‘factorized’ comes from the decision to separate the roles of voltage regulation and voltage conversion in the POL section. Isolation moves downstream to the voltage transformation module (VTM), which is designed to convert the −48 V_DC regulated voltage provided by an immediately upstream pre-regulator module (PRM) to the target voltage. Because the VTM is designed to convert voltage at a fixed ratio, the PRM reacts to regulation commands, tuning its output voltage to meet the demands of the VTM. This architecture allows two different power-conversion topologies to be used, targeting each to the needs of the specific converter, which provides voltage conversion and isolation or regulation.