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UART-Slide4

This picture depicts the block diagram of the 2, 4, and 8 channel UARTs. On one side, there is the x1 lane PCIe interface and on the other side is the standard UART interface. An EEPROM interface is provided for customization of registers, such as programming vendor ID. The clock and Baud Rate Generator can be used to control data rates. Interrupts can be accessed from both the PCIe and UART interfaces.

PTM Published on: 2013-06-18